San Jose, Calif. – May 10, 2004 – Forte Design Systems today announced
Cynthesizer, the
first
behavioral
synthesis product to offer an implementation path from SystemC to RTL,
verification, and co-simulation. Cynthesizer accelerates RTL delivery for
leading-edge integrated circuits and systems-on-chip by automatically
generating optimized RTL code from a C++ / SystemC algorithmic description.
Cynthesizer fills the productivity gap for hardware designers who are
struggling to create increasingly complex chips using previous generation
RTL methods. Designers are able to work at a higher level of abstraction
with Cynthesizer, reducing the amount of code necessary to describe and
implement design functionality.
"The critical enablers for the electronics industry's move to the next
design abstraction level are identical to those that enabled the transition
from gate-level to RTL: a viable language, simulation, and most
importantly, synthesis", said Jacob Jacobsson, Forte's president and chief
executive officer. "Forte's behavioral synthesis breakthrough enables the
use of the next level of design abstraction and serves as an ESL catalyst
by surmounting the complexity issues at 90 nm."
"With 10-100X fewer lines of code than RTL design, more and more project
teams are starting their hardware designs at the behavioral level using
C/C++ algorithms and SystemC models," said Brett Cline, Marketing Vice
President at Forte. "With Cynthesizer, designers can take their existing
algorithms and automatically create verified high quality RTL
implementations in days rather than the months required with conventional
RTL design."
Current RTL design and refinement is time-consuming and error-prone with
the decreases in device geometries. More transistors are now available but
the resources required to evaluate multiple architectural choices and their
respective RTL configurations manually are prohibitive. It's becoming
impossible to design effectively and meet project deadlines. As a result,
designers risk locking into architectural and RTL design descriptions that
cannot be implemented, or do not meet the design objectives. Additionally,
inconsistent RTL coding styles and design approaches within a project team
amplify issues further downstream in the design flow, such as sub-optimal
logic synthesis results and timing closure problems.
Behavioral synthesis allows designers to quickly create hardware from
un-timed high-level models. These models accurately describe the function
but do not specifically schedule or allocate hardware resources as required
when using traditional RTL logic synthesis tools. With behavioral
synthesis, design teams create and verify their designs in an order of
magnitude less time because it eliminates the need to fully schedule and
allocate design resources with existing RTL methods.
Cynthesizer is the only behavioral synthesis tool to offer designers a
complete, automated path from high-level algorithms to RTL, including
synthesis, verification, and co-simulation. It will allow designers to
investigate and automatically validate multiple RTL implementations based
on user directives without modification to the original design.
As a result, designers can use Cynthesizer to automatically produce RTL
in days or weeks instead of months, with quality of results that often
surpasses that of hand coded RTL. Cynthesizer is delivering the foundation
for a synthesizable, routable design and ultimately silicon success.
Using un-timed high-level SystemC models, Cynthesizer is the first
behavioral synthesis product to automatically build a fully timed RTL
hardware implementation based on an external set of constraints created by
the user. Designers can easily and quickly make tradeoffs in chip
performance and area resulting in higher quality designs and superior IP
reuse without modification of the design source. Cynthesizer outputs
industry-standard RTL specifically targeted for a number of downstream
flows and products, such as commonly used simulators and logic synthesis
tools. By using Cynthesizer to control and customize the RTL results,
designers eliminate many issues inherent to conventional RTL design flows,
such as design intent errors, poor quality of results and timing closure
problems.
Cynthesizer includes a unique combination of behavioral synthesis
functions: automation of tasks such as operation scheduling, cycle timing,
control and data path design, resource allocation and RTL generation.
Cynthesizer also includes a complete automation and verification package
which allows results to be immediately verified by reusing a test-bench
with high-level design models, generated RTL, and gate-level models.
Forte is also announcing three new Cynthesizer customers: Fujitsu
Laboratories Ltd, Ricoh and Sony Corporation. Cynthesizer is already being
used for production designs.
"We're extremely happy to announce adoption of Cynthesizer by leading
edge companies such as Fujitsu Laboratories Ltd., Ricoh and Sony
Corporation," said Jacob Jacobsson. "SystemC-based design with Cynthesizer
is providing these customers a path to high-quality silicon in a fraction
of the time of RTL-based design."
Cynthesizer is available today on both Linux and Solaris platforms. Pricing
starts at $250,000 per year for a time-based license. Contact Forte sales
at sales@ForteDS.com for more information.
Forte Design Systems is a leading provider of software products that enable
design at a higher-level of abstraction. Forte's innovative Cynthesizer
behavioral synthesis product allows design teams creating complex
electronic systems from algorithmic designs using ASICs, SoCs, and FPGAs to
significantly reduce their overall design and verification time. Forte is
headquartered at 100 Century Center Court, San Jose, CA 95112. For more
information, visit us at
www.ForteDS.com or see us at DAC 2004 in San Diego, CA in booth 3820.
|